The present inventive concept relates to storage devices, and more particularly to controllers improving the performance of semiconductor memory systems by processing a plurality of instructions in parallel by including a plurality of logical-to-physical address translation central processing units (CPUs) in a multi-channel parallel array structure. The inventive concept also relates to data storage devices and data storage systems including this type of controller, as well as associated data processing methods.
Non-volatile memory is generally characterized by an ability to retain stored data in the absence of applied power. Flash memory is one type of non-volatile memory, and is widely used in computers, memory cards, and a variety of consumer electronics because of is ability to electrically erase stored data on a relatively large block basis. As the use of portable information devices such as cellular phones, portable digital assistants (PDAs), digital cameras has become widespread, flash memory has increasingly been used to replace hard disk drives as a primary data storage component within such devices.
Contemporary flash memory may be classified as NOR flash and NAND flash memories according to the constituent connection structure between memory cells and corresponding bit lines. NOR flash memory is characterized by high speed access (reading) to stored data, but relatively slow writing speeds. As such, NOR flash memory is commonly used as code memory. In contrast, NAND flash memory is characterized by fast writing speed and a low cost per byte ratio. As such, NAND flash memory is particularly well suited for large-capacity storage devices.
Either type of flash memory provides high reading speed at relatively low cost, as compared with the other types of memory devices. However, before data may be written to a flash memory, an erase operation must first be performed before a write operation. Unfortunately, the erase operation and the write operation are applied to different sized blocks of data (i.e., different unit operation sizes) within the flash memory. Namely, the erase unit is larger than the write (or program) unit. This inherent unit operation size mismatch has traditionally impeded the use of flash memory in main memories, and has also hindered the development and use of a general hard disk file system when flash memory is used within an auxiliary storage device.
One response to the unit operation (erase verses write/program) size mismatch is the so-called flash translation layer (FTL). In practical effect, the use of a FTL between the physical memory cells of flash memory and a corresponding file system will hide the operation size mismatch.
To this point in time, conventional solid state drive (SSD) controllers have characteristics, such as a multi-channel parallel array structure, that preclude their use with so-called host command queues, such as a native command queue (NCQ). This conventional disability largely precludes the higher performance being demanded for contemporary semiconductor memory devices and related memory systems. In other words, since conventional SSD controllers include only a single FTL to handle all of the data channels provided by a multi-channel parallel array structure, when a plurality of instructions are processed simultaneously in an NCQ environment, the instruction processing functionality of the FTL restricts overall performance of the constituent semiconductor memory devices, and limits the data access capabilities of the incorporating memory system.